This work is an outcome of the long-term collaboration with Professor Dongmok Hwang at the School of Advanced Materials Science and Engineering of Sungkyunkwan University.  Complementary inverter devices employing both p-and n-type field-effect-transistors (CMOS) are one of the most common building blocks in logic circuit designs. Recently, semiconductor nanowires used as conducting channels in field-effect-transistors (FETs), have attracted a great deal of attention due to their potential to overcome many critical limitations encountered when scaling-down traditional lithography-based thin-film transistor (TFT) devices.

In this work, we first demonstrated a simple method to synthesize highly ordered axially doped p-type and n-type conducting channel regions on a single Si nanowire, where the transport properties of each p-type and n-type conducting channel region can be modulated by efficiently controlling the doping concentration. We also attempted to fabricate the p-n junction diode and CMOS inverter, each of which can be selectively fabricated on a single Si nanowire. Based on high-performance p- and n-type Si NW channel FETs showing especially the low threshold voltages, the fabricated NW CMOS inverters exhibited a low operating voltage (<3 V) while maintaining high voltage gain (~6) and ultra-low static power dissipation (≤0.3 pW) at ±3 V input voltages, thus making them suitable for high-density flexible logic device applications.

While our work deals with one of most advanced issues concerning the device density of nanowire based logic devices, our approach will also have a significant impact on future work to exploit semiconducting one-dimensional or two-dimensional nanostructures including nanowires, nanotubes, nanocables or nanoribbon based CMOS for the next-generation logic circuits in flexible electronic applications.